![]() Complete the timing diagram at Figure 1.10 by drawing the waveform of signals Y1, Y2 and Y3. The circuit of Figure 1.9 contains a D latch, a positive-edge-triggered and a negative edgetriggered D flip-flop. Complete the timing diagram of Figure 1.8 by drawing the waveforms of signals Q0 and Q1. The circuit of Figure 1.7 contains a negative edge-triggered J-K flip flop and a D flip flop. Assume that Y1, Y2 and Y3 are initially SET. The circuit of Figure 1.5 contains a D latch, positive-edge triggered D flip flop, and a negative edge-triggered D flip flop.Ĭomplete the timing diagram of Figure 1.6 by drawing the Assume that Q=0 initially, and draw the Q waveform.ĭesign a combinational circuit using J-K flip-flop that can divide the clock frequency by: two and three. ![]() The waveforms of Figure 1.3 are connected to the circuit of Figure 1.4(a) and Figure 1.4(b). Assume that D is kept LOW and that Q is initially HIGH. ![]() Figure 1.1 shows the positive edge triggered D flip flop, determine the output of Q0, assume output is initially LOW.įor the positive edge-triggered J-K flip-flop with preset and clear inputs in Figure 1.2, determine the Q output for the inputs shown in the timing diagram is initially LOW.Īpply the waveforms of Figure 1.2 to a D flip-flop that triggers on NGT and has active-LOW asynchronous inputs.
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